laboursonline – MCQs, Mock Tests | Gate GATE STUDY MATERIAL /COMPUTER ARCHITECTURE MCQ SET 1

Which one of the following expressions does NOT represent exclusive NOR of x and y?

1. xy + x' y'
2. x ^ y' where ^ is XOR
3. x' ^ y where ^ is XOR
4. x' ^ y' where ^ is XOR

✅ Correct Answer: 3

The simplified SOP (Sum Of Product) form of the boolean expression (P + Q' + R') . (P + Q' + R) . (P + Q + R') is

1. (P'.Q + R')
2. (P + Q'.R')
3. (P'.Q + R)
4. (P.Q + R)

✅ Correct Answer: 2

The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is

1. m2 + m4 + m6 + m7
2. m0 + m1 + m3 + m5
3. m0 + m1 + m6 + m7
4. m2 + m3 + m4 + m5

✅ Correct Answer: 1

What is the minimum number of gates required to implement the Boolean function (AB+C)if we have to use only 2-input NOR gates

1. 2
2. 3
3. 4
4. 5

✅ Correct Answer: 2

If P, Q, R are Boolean variables, then (P + Q')(PQ' + PR)(P'R' + Q') simplifies

1. PQ'
2. PR'
3. PQ' + R
4. PR'' + Q

✅ Correct Answer: 1

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

1. 7
2. 8
3. 9
4. 10

✅ Correct Answer: 3

Consider the following Boolean function of four variables: f(w,x,y,z) = ∑(1,3,4,6,9,11,12,14) The function is:

1. independent of one variables
2. independent of two variables
3. independent of three variables
4. dependent on all the variables

✅ Correct Answer: 2

Let f(w, x, y, z) = ∑(0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are NOT equivalent to f?

1. x'y'z' + w'xy' + wy'z + xz
2. w'y'z' + wx'y' + xz
3. w'y'z' + wx'y' + xyz + xy'z
4. x'y'z' + wx'y' + w'y

✅ Correct Answer: 4

Define the connective * for the Boolean variables X and Y as: X * Y = XY + X' Y'. Let Z = X * Y. Consider the following expressions P, Q and R. P: X = Y⋆Z Q: Y = X⋆Z R: X⋆Y⋆Z=1 Which of the following is TRUE?

1. Only P and Q are valid
2. Only Q and R are valid
3. Only P and R are valid
4. All P, Q, R are valid

✅ Correct Answer: 4

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

1. 2^n line to 1 line
2. 2^(n+1) line to 1 line
3. 2^(n-1) line to 1 line
4. 2^(n-2) line to 1 line

✅ Correct Answer: 3

In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for inputs Ai and Bi are given by: Pi = Ai ⨁ Bi and Gi = AiBi The expressions for the sum bit Si and the carry bit Ci+1 of the look-ahead carry adder are given by: Si = Pi ⨁ Ci and Ci+1 = Gi + PiCi , where C0 is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pi and Gi are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively:

1. 6, 3
2. 10, 4
3. 6, 4
4. 10, 5

✅ Correct Answer: 2

Let k = 2^n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2^n bit decoder. This circuit is equivalent to a

1. k-bit binary up counter
2. k-bit binary down counter
3. k-bit ring counter
4. k-bit Johnson counter

✅ Correct Answer: 3

Consider the equation (123)5 = (x8)y with x and y as unknown. The number of possible solutions is _____ .

1. 1
2. 2
3. 3
4. 4

✅ Correct Answer: 3

Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output. f (x, y, a, b) { if (x is 1) y = a; else y = b; } Which one of the following digital logic blocks is the most suitable for implementing this function?

1. Full adder
2. Priority encoder
3. Multiplexer
4. Flip-flop

✅ Correct Answer: 3

Let X denote the Exclusive OR (XOR) operation. Let ‘1’ and ‘0’ denote the binary constants. Consider the following Boolean expression for F over two variables P and Q: F(P, Q) = ( ( 1 X P) X (P X Q) ) X ( (P X Q) X (Q X 0) ) The equivalent expression for F is

1. P + Q
2. (P + Q)'
3. P X Q
4. (P X Q)'

✅ Correct Answer: 4

Consider a Boolean function f (w, x, y, z). suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i1 = (w1, x1, y1, z1) and i2 = (w2, x2, y2, z2) we would like the function to remain true as the input changes from i1 to i2 (i1 and i2 differ in exactly one bit position), without becoming false momentarily. Let f (w, x, y, z) = ∑(5,7,11,12,13,15). Which of the following cube covers of f will ensure that the required property is satisfied?

1. w'xz, wxy', xy'z, xyz,wyz
2. wxy,w'xz,wyz
3. wx(yz)', xz, wx'yz
4. wzy, wyz, wxz, w'xz, xy'z, xyz

✅ Correct Answer: 1

The hexadecimal representation of 6578 is

1. 1AF
2. D78
3. D71
4. 32F

✅ Correct Answer: 1

The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is

1. BC'D' + A'C'D + AB'D
2. ABC' + ACD + B'C'D
3. ACD' + A'BC' + AC'D
4. A'BD + ACD' + BCD'

✅ Correct Answer: 1

The Boolean function x'y' + xy + x'y is equivalent to

1. BC'D' + A'C'D + AB'D b. c. d.
2. ABC' + ACD + B'C'D
3. ACD' + A'BC' + AC'D'
4. A'BD + ACD' + BCD'

✅ Correct Answer: 4

The Boolean function x'y' + xy + x'y is equivalent to

1. x' + y'
2. x + y
3. x + y'
4. x' + y

✅ Correct Answer: 4

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

1. Q = 0, Q' = 1
2. Q = 1, Q' = 0
3. Q = 1, Q' = 1
4. Indeterminate states

✅ Correct Answer: 4

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?

1. 2
2. 3
3. 4
4. 5

✅ Correct Answer: 2

Which are the essential prime implicants of the following Boolean function? f(a, b, c) = a'c + ac' + b'c

1. a'c and ac'
2. a'c and b'c
3. a'c only
4. ac' and bc'

✅ Correct Answer: 1

Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f = T + R, without using any additional hardware ?

1. R to X, 1 to Y, T to Z
2. T to X, R to Y, T to Z
3. T to X, R to Y, 0 to Z
4. R to X, 0 to Y, T to Z

✅ Correct Answer: 1

A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

1. 4 time units
2. 6 time units
3. 10 time units
4. 12 time units

✅ Correct Answer: 1

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

1. Θ(1)
2. Θ(log n)
3. Θ(n)
4. Θ(n^2)

✅ Correct Answer: 3

A 1-input, 2-output synchronous sequential circuit behaves as follows : Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds. zk - nk = 2. In this case, the output at the k-th and all subsequent clock ticks is 10. nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01. What is the minimum number of states required in the state transition graph of the above circuit?

1. 5
2. 6
3. 7
4. 8

✅ Correct Answer: 1

Let f(A, B) = A' + B. Simplified expression for function f(f(x + y, y)z) is :

1. x' + z
2. xyz
3. xy' + z
4. None of these

✅ Correct Answer: 3

Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is:

1. 0, 1, 3, 7, 15, 14, 12, 8, 0
2. 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
3. 0, 2, 4, 6, 8, 10, 12, 14, 0
4. 0, 8, 12, 14, 15, 7, 3, 1, 0

✅ Correct Answer: 4

Consider the operations f(X, Y, Z) = X'YZ + XY' + Y'Z' and g(X′, Y, Z) = X′YZ + X′YZ′ + XY. Which one of the following is correct?

1. Both {f} and {g} are functionally complete
2. Only {f} is functionally complete
3. Only {g} is functionally complete
4. Neither {f} nor {g} is functionally complete

✅ Correct Answer: 2

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,...) is ________.

1. 0
2. 1
3. 2
4. 3

✅ Correct Answer: 4

The number of min-terms after minimizing the following Boolean expression is _________. [D′ + AB′ + A′C + AC′D + A′C′D]′

1. 1
2. 2
3. 3
4. 4

✅ Correct Answer: 1

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using full adders. The total propagation time of this 4-bit binary adder in microseconds is

1. 19.2 microseconds
2. 18.0 microseconds
3. 12.3 microseconds
4. 16.6 microseconds

✅ Correct Answer: 1

The total number of prime implicants of the function f(w, x, y, z) = Σ(0, 2, 4, 5, 6, 10) is ________.

1. 2
2. 3
3. 4
4. 5

✅ Correct Answer: 2

Given the function F = P′ + QR, where F is a function in three Boolean variables P, Q and R and P′ = !P, consider the following statements. S1: F = Σ (4, 5, 6) S2: F = Σ (0, 1, 2, 3, 7) S3: F = Π (4, 5, 6) S4: F = Π (0, 1, 2, 3, 7) Which of the following is true?

1. S1-False, S2-True, S3-True, S4-False
2. S1-True, S2-False, S3-False, S4-True
3. S1-False, S2-False, S3-True, S4-True
4. S1-True, S2-True, S3-False, S4-False

✅ Correct Answer: 1

What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate?

1. 3
2. 4
3. 5
4. 6

✅ Correct Answer: 2

Using a 4-bit 2’s complement arithmetic, which of the following additions will result in an overflow? (i) 1100 + 1100 (ii) 0011 + 0111 (iii) 1111 + 0111

1. (i) only
2. (ii) only
3. (iii) only
4. (i) and (iii) only

✅ Correct Answer: 2

The number (123456)8 is equivalent to

1. (A72E)16 and (22130232)4
2. (A72E)16 and (22131122)4
3. (A73E)16 and (22130232)4
4. (A62E)16 and (22120232)4

✅ Correct Answer: 1

The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to

1. AC’+AB+A’C
2. AB’+AC’+A’C
3. A’B+AC’+AB'
4. A’B+AC+AB'

✅ Correct Answer: 2

Which of the following expressions is equivalent to (A⊕B)⊕C

1. (A+B+C)(A¯+B¯+C¯)
2. (A+B+C)(A¯+B¯+C)
3. ABC+A¯(B⊕C)+B¯(A⊕C)
4. None of the above

✅ Correct Answer: 3

Using Booth's Algorithm for multiplication, the multiplier -57 will be recoded as

1. 0 -1 0 0 1 0 0 -1
2. 1 1 0 0 0 1 1 1
3. 0 -1 0 0 1 0 0 0
4. 0 1 0 0 -1 0 0 1

✅ Correct Answer: 1

How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?

1. 134
2. 133
3. 124
4. 123

✅ Correct Answer: 4

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is

1. 1
2. 2
3. 4
4. 5

✅ Correct Answer: 3

Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

1. Θ(1)
2. Θ(Log (n))
3. Θ(√ n)
4. Θ(n)

✅ Correct Answer: 2

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _____________

1. -1
2. 2
3. 1
4. -2

✅ Correct Answer: 1

Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation. Then X −Y is _________

1. 1
2. 2
3. 3
4. 0

✅ Correct Answer: 1

The addition of 4-bit, two's complement, binary numbers 1101 and 0100 results in

1. 0001 and an overflow
2. 1001 and no overflow
3. 0001 and no overflow
4. 1001 and an overflow

✅ Correct Answer: 3

Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation ?

1. 11, 00
2. 01, 10
3. 10, 01
4. 00, 11

✅ Correct Answer: 4

The following bit pattern represents a floating point number in IEEE 754 single precision format 1 10000011 101000000000000000000000 The value of the number in decimal form is

1. -10
2. -13
3. -26
4. None of These

✅ Correct Answer: 3

A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:

1. 1, 1, 0
2. 1, 0, 0
3. 0, 1, 0
4. 1, 0, 1

✅ Correct Answer: 2