laboursonline – MCQs, Mock Tests | Gate GATE STUDY MATERIAL /COMPUTER ARCHITECTURE MCQ SET 3

The register which holds the address of the locating to or from which data are to be transferred is known as

1. Index register
2. Instruction register
3. Memory address register
4. Memory data register

✅ Correct Answer: 3

Which one is required while establishing the communication link between CPU and peripherals?

1. Index register
2. Instruction register
3. Memory address register
4. Memory data register

✅ Correct Answer: 4

Which of the following data transfer modes takes relatively more time?

1. DMA
2. Interrupt initiated I/O
3. Programmed I/O
4. Isolated I/O

✅ Correct Answer: 3

Halt operation comes under ………

1. Data transfer
2. Control transfer
3. Conversion
4. I/O transfer

✅ Correct Answer: 2

The CPU initializes the DMA by sending ………

1. The starting address of the memory blocks where data is available or where data is to be stared
2. The word count
3. Control for mode and start the transfer
4. All of the above

✅ Correct Answer: 4

In four – address instruction format, the number of bytes required to encode an instruction is (assume each address requires 24 bits, and 1 byte is required for operation code)

1. 9
2. 13
3. 14
4. 12

✅ Correct Answer: 2

The minimum time delay between the initiations of two independent memory operations is called

1. Access time
2. Cycle time
3. Transfer rate
4. Latency Time

✅ Correct Answer: 2

Consider an algebraic system (A,*), where A is a set of all non-zero real numbers and * is a binary operation defined by A* b = ab/4 then (G*) is a

1. Monoid
2. Semi group
3. Group
4. Abelian group

✅ Correct Answer: 1

A 2 level memory has an average access time of 30 ns with cache and memory access time as 20 ns and 150 ns respectively. What is the hit ratio?

1. 80%
2. 93%
3. 70%
4. 99%

✅ Correct Answer: 2

The following are some of the sequences of operations in the instruction cycle, which one is the correct sequence?

1. PC → address register Data from memory → Data register Data register → IR PC + 1 → PC
2. Address register →PC Data register → Data from memory Data register → IR PC + 1 → PC
3. Data from memory → Data register PC →Address register Data register → IR PC + 1 → PC
4. None of These

✅ Correct Answer: 1

Horizontal micro construction has which of the following attributes? 1) Short formats 2) Limited ability to express parallel micro-operations 3) Considerable encoding of the control information

1. 1 and 2
2. 2 and 3
3. 1,2 and 3
4. None of the these

✅ Correct Answer: 4

The register which keeps track of the execution of a program and which contains the memory address of the instruction currently being executed is known as …………

1. Index – Register
2. Memory address register
3. Program Counter
4. Instruction registers

✅ Correct Answer: 3

Consider the following situation and fill in the blanks: The computer starts the tape moving by issuing a command; the processor then monitors the status of the taps by means of a ………….. When the tape is in the correct position, the Processor issues a ……………

1. Data input, Status, data output command
2. Data input, Status control command
3. Control, Status, Data output command
4. Control, Status, data input Command

✅ Correct Answer: 3

For interval arithmetic best rounding technique use is ………..

1. Rounding to plus and minus infinity
2. Rounding to zero
3. Rounding to nearest
4. None of These

✅ Correct Answer: 1

Assume that the time required for the eight functional units, which operate in each of the eight cycles, are as follows. 5us, 8us, 64s, 10us, 15us, 12us, 6us, 8us Assume that pipe lining adds 1 us, of overhead. Find the speedup versus the single cycle data path.

1. 4.67
2. 4.375
3. 4.44
4. 4.285

✅ Correct Answer: 2

Assembler directives represent……………… 1) Machine instructions to be included in the object program 2) The allocation of storage for constants or program variable

1. Only 1
2. only 2
3. Both 1 and 2
4. Neither 1 nor 2

✅ Correct Answer: 4

The bus system of a machine has the following propagation delay times 40 ns for the signals to propagate through the multiplexers, 90ns to perform the ADD operating in the ALU, 30ns delay in the destination decoder, and 20ns to store the data into the destination register. What is the minimum cycle time that can be used for the clock?

1. 120ns
2. 150ns
3. 960ns
4. 180ns

✅ Correct Answer: 2

The sequence of events that happen during a typical fetch operation is ?

1. PC → Mar →Memory → MOR → IR
2. PC → Memory → MDR → IR
3. PC → Memory → IR
4. PC → Mar → Memory → IR

✅ Correct Answer: 1

In a fully associative cache memory consisting of 256 cache lines of 16 bytes each, a tag field is of 14 bits. Determine the size of cache memory and main memory.

1. 2KB and 128 KB
2. 4kB and 256KB
3. 8KB and 1MB
4. None of the above

✅ Correct Answer: 2

If doubling the cache line length reduces the miss rate to 3 percent, by how much it reduces the average memory access time?

1. 27.1ns
2. 25.75ns
3. 22.2ns
4. 4.85ns

✅ Correct Answer: 1

Consider the following register – transfer language: R₃ ← R₂+ M[R₁ + R₂] Where R₁, R₂ are the CPU registers and M is a memory location in primary memory, which addressing mode is suitable for above register transfer language?

1. Immediate
2. Indexed
3. Direct
4. Displacement

✅ Correct Answer: 2

Booth′s algorithm is used in floating – point

1. Addition
2. Subtraction
3. Multiplication
4. Division

✅ Correct Answer: 3

A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a through put of a. 1⁄3 b. 1⁄7 c. 7 d. 3

1. 1/3
2. 1/7
3. 7
4. 3

✅ Correct Answer: 1

A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a through put of

1. 1/3
2. 1/7
3. 7
4. 3

✅ Correct Answer: 1

What is the control unit’s function in the CPU?

1. To decode program instructions
2. To transfer data to primary storage
3. To perform logical operations
4. To store program instructions

✅ Correct Answer: 1

In a two-level memory hierarchy, the access time of the memory is 12 nanoseconds and the access time of the main memory is 1.5 microseconds. The hit ratio is 0.98. What is the average access time of the two-level memory system?

1. 13.5n sec
2. 42n sec
3. 7.56n sec
4. 76n sec

✅ Correct Answer: 4

Consider the following organization of main memory and cache memory. Main memory: 64k ×16 Cache memory: 256 × 16 Memory is word addressable and block size of 8 words. Determine the size of tag field if the direct mapping is used for transforming data from main memory to cache memory.

1. 5 bits
2. 6 bits
3. 7 bits
4. 8 bits

✅ Correct Answer: 4

A computer system has 4k – word cache organized in a block – set-associative manner, with 4 blocks per set, 64 words per block, memory is word addressable. The number of bits in the SET and WORD fields of the main memory address format is

1. 15, 4
2. 6, 4
3. 7, 6
4. 4, 6

✅ Correct Answer: 4

Booth's coding in 8 bits for the decimal number −57 is:

1. 0 – 100 + 1000
2. 0 – 100 + 100 – 1
3. 0 – 1 + 100 – 10 + 1
4. 00 – 10 + 100 – 1

✅ Correct Answer: 2

What is the equivalent decimal representation for the following radix representation? (34.44)₈

1. (22.56)₁₀
2. (32.56)₁₀
3. (28.5625)₁₀
4. (38.5625)₁₀

✅ Correct Answer: 3

Find x & y values if the following equality is valid. ( X567 )₈ + ( 2YX5 )₈ = ( 71YX )₈

1. 43
2. 34
3. 45
4. 54

✅ Correct Answer: 1

How many digits are required to represent 126 bit binary number in decimal?

1. 32 bits
2. 36 bits
3. 42 bits
4. 46 bits

✅ Correct Answer: 3

Assuming all numbers are in 2’s complement representation, which of the following numbers is divisible by 11111011?

1. 11100111
2. 11100100
3. 11010111
4. 11011011

✅ Correct Answer: 1

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding? (113.+−111.)+7.51 113.+(−111.+7.51)

1. 9.51 and 10.0 respectively
2. 10.0 and 9.51 respectively
3. 9.51 and 9.51 respectively
4. 10.0 and 10.0 respectively

✅ Correct Answer: 1

(1217)₈ is equivalent to

1. (1217)₁₆
2. (028F)₁₆
3. 2297)₁₀
4. (0B17)₁₆

✅ Correct Answer: 2

P is a 16 – bit signed integer. The 2’s complement representation of P is (F87B)₁₆. The 2’s complement representation of 8 * p is

1. (C3D8)₁₆
2. (187B)₁₆
3. (F878)₁₆
4. (987B)₁₆

✅ Correct Answer: 1

Find the radix 5 representation for the following decimal representation: (39)₁₀ = ( ) ₅

1. (134)₅
2. (124)₅
3. (114)₅
4. (144)₅

✅ Correct Answer: 2

Find the value of radix r, with the following equality is matached. √(21)ᵣ = (11)ᵣ

1. 8
2. 7
3. 10
4. >2

✅ Correct Answer: 4

How many bits are needed to represent 20 digit decimal number in binary?

1. 62bits
2. 60 bits
3. 64bits
4. 66 bits

✅ Correct Answer: 2

Consider the following subtraction and Identify the correct answer. (C012.25)₄ – (10111001110.101)₈

1. (135103.412)₈
2. (564411.412)₈
3. (564411.205)₈
4. (135103.205)₈

✅ Correct Answer: 1

Let A = 11111010 and B = 00001010 be two 8 – bit 2's complement numbers. Their product in 2's complement is

1. 11000100
2. 10011100
3. 10100101
4. 11010101

✅ Correct Answer: 1

The range of integers that can be represented by an n – bit 2's complement number system is

1. – 2ⁿ⁻¹ to (2ⁿ⁻¹ -1)
2. – (2ⁿ⁻¹ -1) to (2ⁿ⁻¹ -1)
3. – 2ⁿ⁻¹ to 2ⁿ⁻¹
4. – (2ⁿ⁻¹ +1) to (2ⁿ⁻¹ -1)

✅ Correct Answer: 1

The switching expression corresponding to f(A, B,C, D) = Σ (1, 4, 5, 9, 11,12) is

1. BC'D' + A'C'D + AB'D
2. ABC' + ACD + B'C'D
3. ACD' + A'BC' + AC'D
4. A'BD + ACD' + BCD'

✅ Correct Answer: 1

What is the maximum number of different Boolean functions involving n boolean variables?

1. n²
2. 2ⁿ
3. 2²ⁿ
4. 2n²

✅ Correct Answer: 3

How many Boolean functions are possible with 2 trinary variables?

1. 256
2. 512
3. 1024
4. 128

✅ Correct Answer: 2

How many minimum 2-input nor gates are needed to realize A+BC?

1. 2
2. 3
3. 4
4. 5

✅ Correct Answer: 2

Which of the following statement is true regarding ‘HAZARD’?

1. A digital circuit exhibits temporary mal-function. If the i/p’s are having un-even propagation delays.
2. The permanent mal-function is due to the open circuit (or) short circuit of connection lead to the orbit
3. The Hazard can be struck at 0 (or) 1
4. All

✅ Correct Answer: 4

The min term expansion of f(P,Q,R) = PQ + QR̅ + PR̅ is

1. m₂+m₄+m₆+m₁
2. m₀+m₁+m₃+m₅
3. m₀+m₁+m₆+m₁
4. m₂+m₃+m₄+m₅

✅ Correct Answer: 1

How many Boolean functions are possible with 3 Boolean variables such that the number of min terms are either one or two?

1. 18
2. 8
3. 26
4. 36

✅ Correct Answer: 4

Which of the following statement is FALSE regarding functionally completeness, (FC).

1. A Boolean function is said to be FC if it realizes all the basic operations (AND, OR, NOT)
2. A function can be FC if it reduces to another function i.e.., already known as FC
3. All the universal operations are FC
4. All the universal operations are FC

✅ Correct Answer: 4

Which of the following is the minimization expression for A+A'B+A'B'C+A'B'C'D?

1. ABCD
2. A+B) (C+D)
3. A+B+C+D
4. 1

✅ Correct Answer: 3

Consider a hypothetical k-map in which essential prime implicants covering all the min – terms except two. Each of the left over min – term is covered by 3 different redundant prime implicants. What would be the no of minimal expressions denoted by the map?

1. 3
2. 8
3. 9
4. 16

✅ Correct Answer: 3

The literal count of a Boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (x y + x z) is 4. What are the minimum possible literal counts of the product – of – sum and sum – of – product representations respectively of the function given by the following karnaugh map? Here, x denotes “don’t care”.

1. (11,9)
2. (9,13)
3. (9,10)
4. (11,11)

✅ Correct Answer: 3

What are the essential prime implicants of the following Boolean functions? F (a, b, c) = a'c + ac' + b'c

1. a'c and ac'
2. a'c and b'c
3. a'c only
4. ac' and b'c

✅ Correct Answer: 1

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

1. 4 time units
2. 6 time units
3. 10 time units
4. 12 time units

✅ Correct Answer: 2