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Analytical Instrumentation MCQ Question Set 27
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1. TTL stands for _____
Transistor-triode-logic
Triode-transistor-logic
Triode-triode-logic
Transistor-transistor-logic
2. Which of the following is correct for digital devices?
Single stable logic level
Double stable logic level
Triple stable logic level
Infinite stable logic level
3. Which of the following gate act as inverter?
AND gate
OR gate
NOT gate
NAND gate
4. Unity-gain amplifier is the equivalent of ______
Inverter
Driver
Amplifier
Rectifier
5. Which of the following represents ‘inhibit’ gate?
AND gate
NAND gate
OR gate
NOR gate
6. In op-amp IC negative saturation is defined by _______
Logic High
Logic Low
Inverter
None of the mentioned
7. Which of the following is equivalent to voltage-controlled switch?
Inverter gate
Drier gate
Transmission gate
None of the mentioned
8. OR gate has high output if ______
One input is low
One input is high
All of the mentioned
None of the mentioned
9. Driver has high output level when_______
Input is high
Input is high
All of the mentioned
None of the mentioned
10. One flip-flop unit can store __________ of data.
One nibble
One bit
One byte
One kilo-bit
11. SR flip-flop stands for _______
State-reset
Set-reset
Set-recovery
Set-reset
12. Which of the following represents D flip flop?
Data flip flop
Delay flip flop
Direct flip flop
Decode flip flop
13. SR flip flop have undefined state when________
Both inputs are low
Both inputs are high
One input is low
None of the mentioned
14. Latch is a circuit which operates according to a clock pulse.
True
False
all of the above
None of the mentioned
15. Race around condition can be rectified by ________
SR flip flop
JK flip flop
JK master slave flip flop
D flip flop
16. Which of the following is an application of flip-flop?
Shift register
Latch
Gates
All of the mentioned
17. If SET pin is active, output becomes _____
High
Low
Undefined
None of the mentioned
18. In SR flip flop if both inputs are low, output becomes ______
High
Low
No change
Undefined
19. Which of the following is not a sequential circuit?
Flip flop
Counter
Logical gate
Shift register
20. Which of the following is correct for data transfer in shift register?
Serial manner
Parallel manner
Both serial and parallel
None of the mentioned
21. Which of the following is correct for serial mode shift register?
One bit per clock pulse
One byte per clock pulse
Two bit per clock cycle
Unpredictable
22. Which of the following flip flops can be used for making shift registers?
T flip flop
JK flip flop
SR flip flop
All of the mentioned
23. Which of the following is not a valid BCD?
0110
0111
1000
1010
24. Which of the following have high propagation delay?
Synchronous counter
Asynchronous counter
Both have the same propagation delay
Both have an unpredictable propagation delay
25. Asynchronous counters does not need a clock pulse.
True
False
all of the above
None of the mentioned
26. In a BCD counter count 1010 corresponds to _______
Ten
Zero
Two
One
27. What will be the final count value if 10 flip flops are used?
100
1024
1023
99
28. Read in data of shift register will be ______
Serial
Parallel
Both serial and parallel
Unpredictable
29. Each flip flop in shift register act as________
Frequency multiplier
Frequency divider
Frequency doubler
Frequency adder
30. A decoder converts n inputs to __________ outputs.
n
n2
2n
nn
31. Which of the following are building blocks of encoders?
NOT gate
OR gate
AND gate
NAND gate
32. Which of the following can be represented for decoder?
Sequential circuit
Combinational circuit
Logical circuit
None of the mentioned
33. BCD to seven segment conversion is a _____
Decoding process
Encoding process
Comparing process
None of the mentioned
34. Which of the following is a decoder IC?
7890
8870
4047
4041
35. DTMF stands for _______
Dual Tone Magnetic Frequency
Double Tone Magnetic Frequency
Dual Tone Multiple Frequency
Dual Tone Mechanical Frequency
36. Invalid BCD can be made to valid BCD by adding with ________
0101
0110
0111
1001
37. Decoder is constructed from _________
Inverters
AND gates
Inverters and AND gates
None of the mentioned
38. Which of the following represents a number of output lines for a decoder with 4 input lines?
15
16
17
18
39. Decoders and Encoders are doing reverse operation.
True
False
all of the above
None of the mentioned
40. Which of the following are used in DAC?
Ladder network
Successive approximation technique
Both Ladder and successive approximation technique
None of the mentioned
41. Which of the following is an indication by settling time?
Accuracy of conversion
Speed of conversion
Precision in conversion
All of the mentioned
42. Filling data between impulses in DAC is known as _______
Reconstruction
Sampling
Interpolation
None of the mentioned
43. Which of the following represents over sampling DAC?
PWM DAC
Delta-sigma DAC
Binary weighted DAC
Switched resistor DAC
44. Which of the following is a binary weighted DAC?
R-2R ladder DAC
PWM DAC
Switched resistor DAC
Sampling DAC
45. Segmented DAC uses ____________
Thermometer coded principle conversion only
Binary weighted principle only
Both thermometer coded and Binary weighted principle
None of the mentioned
46. Ability of analog output to move only in the direction of digital input move is known as _______
Monotonicity
Resolution
Sampling rate
Dynamicity
47. Dynamic range is expressed in _______
Volts
Ampere
Hz
Decibel
48. Thermal noise is absent in DAC.
True
False
all of the above
None of the mentioned
49. SFDR stands for _______
Spurious free dielectric range
Signal free dynamic range
Spurious free dynamic range
None of the mentioned
50. Typical conversion speed of ADC is ______
Less than 1µs
Less than 100 µs
Less than 500 µs
Greater than 1000 µs
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